Programmable logic devices of the types described generally in Spencer U.S. Pat. No. 3,566,153, Birkner et al. U.S. Pat. No. 4,124,899, Hartmann et al. U.S. Pat. No. 4,609,986, Hartmann et al. U.S. Pat. No. 4,617,479 and Hartmann et al. U.S. Pat. No. 4,713,792 can be implemented using fuses, anti-fuses, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) or flash EPROM as their programmable elements. Such devices are typically set up as basically orthogonal arrays of "bit lines" and "word lines" which can be programmably interconnected to achieve a desired logical result. It is known that the programmable interconnections in such devices can be programmed by addressing the appropriate bit lines and word lines, and transferring the desired programming data to the interconnections by applying to the selected word lines and bit lines a predetermined programming voltage--e.g., a voltage significantly higher than that encountered in the normal logical operation of the device. When the programmable elements are any of the above-mentioned types of EPROM using floating gate field effect transistors, the high programming voltages trap electrons on the floating gate of the transistor, raising the threshold voltage, as seen from the control gate of the transistor, needed to turn the transistor on. It is desirable that the threshold be raised as high as possible above normal operating voltage, to provide a guard band effect in case of voltage variations during normal operation.
Traditionally, programmable logic devices have been programmed by passing once through the array and sequentially programming each programmable interconnection, or "cell." In the earliest known programming scheme, the programming voltages were applied once to each cell for relatively long periods--e.g., 45-50 msec. In a later programming scheme, shorter pulses were used--e.g., 1 msec, and each cell received a plurality--e.g., up to fifteen--pulses. In this later scheme, the cell was verified after each pulse, and if that cell had already reached the desired voltage, programming of that cell was discontinued and the process continued on the next cell.
In using the prior schemes, it has been observed that certain devices could not be programmed because one or more cells would not reach the desired voltage. This was true even if very long pulses, or a high number--even higher than the normal number of repetitions--of pulses, were applied. Other devices could be programmed if very long pulses or a high number of pulses were applied. However, such devices would fail the normal programming procedure and require special handling. In addition, the more one tried to program the difficult cells in such devices, the more one stressed the entire device and disturbed "half-selected" bits--i.e., other cells which shared either the bit line or the word line of the cell being programmed.
It would be desirable to be able provide a method of programming programmable logic devices that is faster than known programming methods, that achieves the highest possible programmed voltage, and that would decrease the number of failed devices.
It would also be desirable to be able to provide such a programming method that would minimize the stress on the device and the disturbance of already programmed cells.